Thursday, 22 October 2015

Clock Latencies

Source latency: 

The delay from the clock origin point to the clock definition point in the design.
It is the insertion delay external to the circuit which we are timing. It applies to only primary clocks.


Network Latency: 

The delay from the clock definition point to the clock pin of the register
It is the internal delay for the circuit which we are timing (the delay of the clock tree from the source of the clock to all of the clock sinks).


I/O latency

If the flop of the block is talking with another flop outside the block, clock latency (network) of that flop will be the i/o latency of the block.

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