Thursday, 22 October 2015

Latch Vs Flipflop (Advantages and Disadvantages)

Advantages and Disadvantages

1. In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:”if” and “case” statements. This should be avoided sa latches are more prone to glitches.

2. Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .

3. Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.

4. Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using “enable” and “scan_enable” signals as input and feed the output to the enable port of the latch. 

5. Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.

6. If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team.

7. Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch.

8. Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

1 comment:

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