STA calculates the delay along each timing path by determining the Gate delay and Net delay.
1. Gate Delay : Amount of delay from the input to the output of a logic gate. It is calculated based on 2 parameters.
---Input Transition Time
---Output Load Capacitance
2. Net Delay : Amount of delay from the output of a gate to the input of the next gate in a timing path. It depends on the following parameters.
--Resistance of net
During STA, the tool calculates timing of the path by calculating:
1. Delay from input to output of the gate (Gate Delay).
2. Output Transition Time -> (which in turn depends on Input Transition Time and Output Load Capacitance)