Friday, 9 October 2015

Scan Chain Reordering

    Scan Chain

    Scan chain is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.
    1. Scan_in and scan_out define the input and output of a scan chain. In a full scan mode usually each input drives only one chain and scan out observe one as well .
    2. A scan enable pin is a special signal that is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register.
    3. Clock signal which is used for controlling all the FFs in the chain during shift phase and the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the state of every flip-flop can be read out.

Scan Chain Reordering

Scan chains are long shift registers for ATPG purposes. Since these chains are stitched pre-layout, these need not be layout friendly. Without re-ordering of chains, scan chains contribute to a long total wirelength. From a routability perspective it is important to reduce total wirelength. This reduces (limited) metal demand and acts to reduce congestion. Stray chains (unordered) may require repeaters and an increase in utilization. Although timing issues may not be expected since the chains are merely shift paths running at low atpg shift frequency, this might be an issue if chain quality is too poor.

1 comment:

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