Latch Up Effect

A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.

A single event latch-up is a latch-up caused by a single event upset, typically heavy ions or protons from cosmic rays or solar flares.

The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.

How to Prevent Latch Up Effect

• by adding tap wells, for example in an Inverter for NMOS add N+ tap in n-well and conncet it to Vdd, and for PMOS add P+ tap in p-substrate and connect it to Vss. 
• an increase in substrate doping levels with a consequent drop in the value of  Rs.
• reducing Rp by control of fabrication parameters and by ensuring a low contact resistance to Vss.
• By Providing Guard rings