Thursday 22 October 2015



  • It is difference between the desired arrival times and the actual arrival time for a signal. 
  • Slack time determines [for a timing path], if the design is working at the desired frequency. 
  • Positive Slack indicates that the design is meeting the timing and still it can be improved. 
  • Zero slack means that the design is critically working at the desired frequency. 
  • Negative slack means , design has not achieved the specified timings at the specified frequency. 
  • Slack has to be positive always and negative slack indicates a violation in timing.

Required time: 

The time within which data is required to arrive at some internal node of the design. Designer specify this value by setting constraints.

Arrival Time: 

The time in which data arrives at the internal node. It incorporates all the net and logic delays in between the reference input point and the destination node. 

 Setup Slack = Required time - Arrival time
 Hold slack = Arrival time - Required time 

 Setup Slack: 

Amount of margin by which setup requirements are met. 

TCL = Total combinational delay in a pipe-lined stage 

TRC = RC delay of interconnects 

TC-Q = Clock to output delay 

Tarrival = Arrival time (at node) 

Tcycle,min = Minimum Achievable clock cycle 

To meet the setup requirements the following equation must be satisfied. 

Tslack,setup = Tcycle – Tarrival - Tsetup (For all Paths ) 

Here Tarrival= TCL + TRC + TC-Q

Hold Slack: 

Amount of margin by which hold time requirements are met. 

Tarrival >= Thold 

Tarrival – Thold = Thold,slack 

Thold,slack = TCL + TRC + TC-Q - Thold

  • The Negative value of Hold Slack means signal value propagates from one register to next, too fast that it overrides the old value before that can be detected by the corresponding active clock edge. 
  • The Clock frequency variation doesn’t effects the Hold time or the Hold slack so it is critical to fix the Hold time violations in a design prior to the setup violation if both exists simultaneously


  1. it can be better if you will explain by some small circuit design and specified each term from circuit

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  3. How to reduced setup time and hold time (slack) violations in physical design