Sunday, 11 October 2015

Timing Paths

Timing Paths

The different kinds of paths when checking the timing of a design are as follows.

1. Input ports/pin --> Sequential element (Register).
2. Sequential element (Register) --> Sequential element (Register)
3. Sequential element (Register) --> Output Pin/Port
4. Input ports/pin -->  Output Pin/Port



The static timing analysis tool performs the timing analysis in the following way.
  1. STA Tool breaks the design down into a set of timing paths. 
  2. Calculates the propagation delay along each path. 
  3. Checks for timing violations (depending on the constraints e.g. clock) on the different paths and also at the input/output interface.

Timing Analysis is performed by splitting the design into different paths based on: 


  • Start Points 
  • End points  

  • Start points comprise of:
    A clock, a primary input port, a sequential cell, a clock input pin of a sequential cell, a data pin of a level-sensitive latch, or a pin that has an input delay specified.
  • End points comprise of:
    A clock, a primary output port, a sequential cell, a data input pin of a sequential cell, or a pin that has an output delay specified. 

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