Thursday, 22 October 2015

Hold Time

Hold time:

  • Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop. 
  • Or in short I can say that the amount of time the synchronous input (D) must be stable after the active edge of clock. 
  • The Time after clock pulse where data input is held stable is called hold time.








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