Sunday 11 October 2015

Timing Exceptions

Timing exceptions are nothing but constraints which don’t follow the default when doing timing analysis. The different kinds of timing exceptions are

1. False path: If any path does not affect the output and does not contribute to the delay of the circuit then that path is called false path.

2. Multi-cycle Path Multicycle paths in a design are the paths that require more than one clock cycle. Therefore they require special Multicycle setup and hold-time calculations

3. Min/Max Path : This path must match a delay constraint that matches a specific value. It is not an integer like the multicycle path. For example:Delay from one point to another max: 1.67ns; min: 1.87ns

4. Disabled Timing Arcs : The input to the output arc in a gate is disabled.
 For e.g. 3 input and gate (a, b, c) and output (out). If you want you can disable the path from input ‘a’ to output ‘out’ using disable timing arc constraint.

Clock Path:

Please check the following figure:

In the above fig its very clear that for clock path the starts from the input port/pin of the design which is specific for the Clock input and the end point is the clock pin of a sequential element. In between the Start point and the end point there may be lots of Buffers/Inverters/clock divider.

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