Detailed list of Topics, Note this topics will be timely updated as per requirement, any feedback and suggestions are welcome (please write on comment section or send mail us to vlsijunction@gmail.com)
PreRequisite
- CMOS Fundamentals
- Wafer Fabrication Techniques
- Basic Linux Commands
- Digital Electronics Fundamentals
- Moore's Law
- Basic Synthesis Flow
- Physical Design Introduction
- Physical Design Flow
- Important Input Files
- Sanity Checks
- Floor Planning
- Power Planning Basics
- Placement
- Routing
- CTS
- STA
- Physical Verification
FloorPlannig topics
- Blockages
- Aspect Ratio
- Design Netlist
- Some Basic Rules For Placing Macros
- IO Placement / Pin placement
- Core Utilization
- Die Area calculation
- Design Exchange Format (DEF) Files
- Library Exchange Format (LEF) Files
- Macro Placement Tips
Power planning
Low Power Design Techniques
Placement
CTS
Routing
STA
- Setup Time
- Hold Time
- Slack
- Clock Latencies
- Clock Skew
- Recovery and Removal Time
- Timing Exceptions
- Onchip Variation (OCV)
- Advance Onchip Variation
- Signal Integrity
- Statistical static timing analysis
- Topics Covered in Static Timing Analysis (STA)
- Parametric On chip variation (POCV)
- Asynchronous Path
- Input To STA Tools
- STA vs DTA
- Timing Paths
- Propagation Delay Calculations
- Clock Gating
- Jitter
- Unateness
- Signal Integrity Effects
- Virtual Clock
Sign Off Check
DFM
Tools Guide and References
Interview Questions
Physcial Design
- Physical Design Interview Question Part 1
- Physical Design Interview Question Part 2
- Physical Design Interview Question Part 3
- Physical Design Interview Question Part 4
- Physical Design Interview Question Part 5
- Physical Design Interview Question Part 6
- Physical Design Interview Question Part 7
- Physical Design Interview Question Part 8
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